-- Scott Sirowy -- February 7th, 2007 -- Sample game framework using a BRAM video screen library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is Port ( clk : in std_logic; reset : in std_logic; hsync : out std_logic; --vga signals vsync : out std_logic; red_out : out std_logic; --color signals grn_out : out std_logic; blue_out : out std_logic ); end top; architecture struct of top is component vga_timings is port( reset : in std_logic; clock : in std_logic; -- 50MHz clock assumed hsync : out std_logic; vsync : out std_logic; hcount : out std_logic_vector(9 downto 0); vcount : out std_logic_vector(8 downto 0) ); end component; component screen is Port ( clock : in std_logic; reset : in std_logic; address : in std_logic_vector(11 downto 0); data : out std_logic_vector(3 downto 0) ); end component; component rgb_read is Port ( hcount : in std_logic_vector(9 downto 0); vcount : in std_logic_vector(8 downto 0); input : in std_logic_vector(3 downto 0); ram_addr : out std_logic_vector(11 downto 0); red : out std_logic; blue : out std_logic; green : out std_logic ); end component; signal hcount_sig : std_logic_vector(9 downto 0); signal vcount_sig : std_logic_vector(8 downto 0); signal video_address : std_logic_vector(11 downto 0); signal rgb_in : std_logic_vector(3 downto 0); begin my_vga: vga_timings port map( reset => reset, clock => clk, hsync => hsync, vsync => vsync, hcount => hcount_sig, vcount => vcount_sig ); screen_mem: screen port map( clock => clk, reset => reset, address => video_address, data => rgb_in ); color_mapper: rgb_read port map( hcount => hcount_sig, vcount => vcount_sig, input => rgb_in, ram_addr => video_address, red => red_out, blue => blue_out, green => grn_out ); end struct;