Tutorial: Using Xilinx ISE8

Step 1

For this tutorial, we will create a simple design that lights up an LED when a button is pressed. To begin, launch the Project Navigator.

If you are not prompted to create a new project, start the new project wizard by selecting New Project in the File menu.
Enter a desired Project Name (e.g. lab1).
Set the Project Location as needed.
Click Next.

Step 2

We will now specify the FPGA we will be synthesizing for. These values can be derived by looking at the labels imprinted on the FPGA chip on the Digilab board.

Choose the following Device & Design Flow settings: Spartan3E, xc3s500e, fg320, -4.
Click Next and Finish until you have exited the New Project Wizard.

Step 3

You are now viewing the Project Navigator. The Sources in Project section will automatically organize your VHDL elements in a tree. The Processes for Source pane allows you to perform various processes such as synthesis or device programming, view reports, and access useful tools. The bottom pane contains console output - notice the "Warnings" and "Errors" tabs. The right, tabbed pane displays any files or documents you have opened.

We will now create a new VHDL entity for our project.

Right-click on the chip name and select New Source.

Step 4

Select VHDL Module.
Name the new VHDL file as desired.
Click Next.

It is necessary to fill in at least one port in the wizard screen for your new module. If you don't add a port through the following screen, Xilinx will not recognize your new module in the synthesis stage.

Step 5

Delete the auto-generated contents of the new file and replace it with the following code:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity passthrough is port( button: in STD_LOGIC; led: out STD_LOGIC ); end passthrough; architecture bhv of passthrough is begin led <= button; end bhv;

Step 6

Now we will create a constraints file that specifies what portions of the design are connected to what pins on the FPGA.

Verify that your entity is selected in the Sources in Project pane.
Expand the User Constraints option in the Processes for Source pane.
Double-click Edit Constraints. Answer Yes if prompted about creating a new UCF file.
Copy the following definitions into your new UCF file:

You can also use the Assign Package Pins tool to graphically map ports, but it is typically faster to type out the contraints manually.

Step 7

We will now generate a bitstream from our design that is suitable for downloading to the Digilab board.

Double-click the Generate Programming File process.

Synthesis and Implementation will be automatically performed if needed. Notice in the top left of the screen that by default you are in a menu option called 'Sources For: Synthesis/Implementation". You need to keep it in this option in order to see the correct screens for synthesis. Alternately, you can double-click on the preceeding processes in sequence. If everything ran to completion without any problems, you will see a green checkmark next to the process name. Otherwise, you may see an exclamation point or an "X". An exclamation point indicates a warning occured during that step while a red "X" appears when an error occured. You can expand the tree for each step and double-click on the appropriate report to learn more about any warnings or errors.

Step 8

We will now setup the iMPACT tool, preparing it for downloading our bitstream.

Expand the Generate Programming File process.
Double-click on Configure Device (iMPACT) to launch the downloading tool.
Verify that your Digilab board is powered on and connected to your PC's USB port.
Select Boundary-Scan Mode and click Finish.

You should receive a message about a device being detected. If your board was not detected, power-cycle your board, exit iMPACT, and redo this step.

There are actually 3 chips on the new Spartan 3E boards, one of which will concern us for this lab. By default a screen will pop up to assign each chip a configuration file. For the first screen, assign your .bit file, and for the next two screens, select Bypass. This will ensure that the other two chips are not programmed.
If you weren't prompted to select a .bit file, right click on the image of the chip and select Assign New Configuration File.
In the file dialog box, find and Open your top-level .bit file.
If you receive a warning about a different device detected, click Yes.

Step 9

Right click the first chip in the chain (the xs3s500e), and click Program
Once programmed, a message should pop up saying the programming succeeded
Verify the circuit worked by pressing the button on your board, and seeing if the light turns on

Tutorial: Using Xilinx ISE 8